Three student researchers spent summer 2026 working on posit arithmetic
and RISC-V hardware using open lab infrastructure hosted in San Jose.
All three papers were conditionally accepted at
CoNGA 2026 (Conference on Next Generation Arithmetic),
co-located with SC26 in Chicago. Camera-ready deadline: October 28, 2026.
Papers
Exact Accumulation Improves the Inner Product but Not the Attainable Accuracy of Conjugate Gradient
Gurleen Kaur Kansray
—
Guru Nanak Dev Engineering College, I.K. Gujral Punjab Technical University
with James Quinlan (University of Southern Maine),
E. Theodore L. Omtzigt (Stillwater Supercomputing),
Paul Sherman (RISC-V International)
Strong Accept + 2× Accept
The posit quire improves inner product accuracy by up to 1000× in conjugate gradient
sparse linear solvers — yet final solution accuracy changes surprisingly little.
Iterative refinement is where the quire earns its keep.
Tested across 20+ random seeds and 13 sparse matrices from SuiteSparse,
all runs on the Pioneer.
Closing the Performance Gap of Posit Arithmetic Hardware: A RISC-V Fife Core Case Study
Bola Yosry Warsy
—
Cairo, Egypt
with E. Theodore L. Omtzigt (Stillwater Supercomputing),
Joshua Gyllinsky,
Paul Sherman (RISC-V International)
2× Accept
Branch prediction on the open-source Fife RISC-V core reduces clock cycles
by 36% for loop-intensive programs. Bounded posit (b-posit) synthesis
cuts critical path by 28%, narrowing the speed gap with IEEE 754 hardware.
A Motif-Indexed Dataset of HPC Numerical Kernel Value Distributions for Porting HPC Applications to Posits
Shree Bhargav Komanabelli
—
Iowa State University
Strong Accept + Accept
A systematic framework for selecting posit format parameters (n, es) before
committing to a port. Applied to SPICE, GROMACS, and CHARMM using
Berkeley motif classification and runtime value distribution profiling.
Related Work
Depth or Breadth? Flat128 Arithmetic and the RV128 Opportunity
Paul Sherman (RISC-V International) &
Kurt Keville (MIT / Posit Foundation)
Flat128 treats a 128-bit register as a uniform fixed-point significand with
compiler-managed binary point — no exponent overhead, bitwise-reproducible
accumulation across threads and NUMA nodes. IEEE 754 double diverges by
up to 8.9×10−16 at K=4096; flat128 stays exact.
Submitted to CoNGA 2026.